Conventional MOS technology employs transistor gates including a metal layer over a doped polysilicon layer that is, in turn, over a gate dielectric. Conventional CMOS uses complementary n-channel and p-channel MOS transistors. Since CMOS includes both n-channel and p-channel gates, the gates typically exhibit different work functions depending upon whether the channel exhibits n-type or p-type conductivity. For example, p-channel transistor gates typically exhibit a work function of from 4.5 to 5.2 electron volts (eV) and n-channel transistor gates typically exhibit a work function of from 3.8 to 4.5 eV. Work function in polysilicon components of transistor gates may be controlled and/or optimized by the quantity and type of conductivity dopant. Accordingly, transistor gates containing polysilicon may be optimized to a work function corresponding to the respective n-channel and p-channel regions in CMOS.
Unfortunately, polysilicon, even when doped, generally exhibits a lower conductivity in comparison to the conductivity exhibited by many metal layers. Accordingly, obtaining desirable performance in CMOS devices often includes providing a strapping layer exhibiting a higher conductivity than the doped polysilicon. Exemplary compositions for strapping layers include elemental metal or metal silicide.
It would be an improvement to identify suitable materials and processing methods that use materials with a higher conductivity than conventional doped polysilicon, but are still optimizable to the work function characteristics desired for CMOS. Herein lays the difficulty, since known metal gates of such higher conductivity exhibit inherent work function characteristics that are not conventionally known to be optimizable. N-channel metal gates and p-channel metal gates may be deposited separately using different materials to obtain the different work functions. Even though multiple depositions of materials exhibiting different work functions might be used, such an approach adds significantly to the complexity of processes for producing CMOS devices. A simpler approach would be more advantageous.